By Rezaur Rahman
Intel® Xeon Phi™ Coprocessor structure and instruments: The advisor for program builders presents builders a entire advent and in-depth examine the Intel Xeon Phi coprocessor structure and the corresponding parallel facts constitution instruments and algorithms utilized in a few of the technical computing purposes for which it truly is compatible. It additionally examines the resource code-level optimizations that may be played to use the strong positive factors of the processor.
Xeon Phi is on the center of world’s quickest advertisement supercomputer, which due to the vastly parallel computing features of Intel Xeon Phi processors coupled with Xeon Phi coprocessors attained 33.86 teraflops of benchmark functionality in 2013. Extracting such stellar functionality in real-world purposes calls for a cosmopolitan knowing of the complicated interplay between parts, Xeon Phi cores, and the functions operating on them.
In this e-book, Rezaur Rahman, an Intel chief within the improvement of the Xeon Phi coprocessor and the optimization of its functions, offers and info the entire positive aspects of Xeon Phi middle layout which are suitable to the perform of program builders, corresponding to its vector devices, multithreading, cache hierarchy, and host-to-coprocessor verbal exchange channels. construction in this beginning, he indicates builders the way to remedy real-world technical computing difficulties through picking out, deploying, and optimizing the to be had algorithms and information constitution choices matching Xeon Phi’s features. From Rahman’s functional descriptions and vast code examples, the reader will achieve a operating wisdom of the Xeon Phi vector guide set and the Xeon Phi microarchitecture wherein cores execute 512-bit guide streams in parallel.
What you’ll learn
How to calculate theoretical Gigaflops and bandwidth numbers at the and degree them via code segment
How to estimate latencies in fetching facts from diversified cache hierarchies, together with reminiscence subsystems
How to degree PCIe bus bandwidth among the host and coprocessor
How to take advantage of strength administration and reliability positive factors outfitted into the hardware
How to choose and control the easiest instruments to music specific Xeon Phi applications
Algorithms and knowledge buildings for optimizing Xeon Phi performance
Case stories of real-world Xeon Phi technical computing functions in molecular dynamics and fiscal simulations
Who this booklet is for
This e-book is for builders wishing to layout and enhance technical computing purposes to accomplish the top functionality on hand within the Intel Xeon Phi coprocessor undefined. It presents a fantastic base at the coprocessor structure, in addition to set of rules and information constitution case experiences for Xeon Phi coprocessor. The ebook can also be of curiosity to scholars and practitioners in laptop engineering as a case learn for hugely parallel middle microarchitecture of contemporary day processors.